This application is based upon and claims priority of Japanese Patent Application No. 2002-147008, filed on May 22, 2002, the contents being incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor device, and particularly to a semiconductor device with fuses for repairing a defect found after production.
2. Description of the Related Art
A class of semiconductor devices containing memory circuits have a redundant memory cell array to repair a memory defect that is found after production. The repair process decouples the defective memory cell array from other circuits by blowing laser-programmable fuses provided in the device, and recovers its function with the redundant array that is now activated. In the chip structure, fuse patterns are each arranged under a rectangular guard ring, so that a laser beam directed to the inside of the guard ring will hit the intended fuse pattern. FIGS. 6(A) and (B) illustrate a guard ring and a fuse pattern formed on a semiconductor device. Specifically, FIG. 6(A) is a plan view, and FIG. 6(B) is a cross-sectional view taken along the line 100xe2x80x94100 in FIG. 6(A).
As shown in FIGS. 6(A) and (B), the semiconductor device has an insulating film layer 41 formed on a semiconductor substrate 40, and a fuse pattern 42 is placed in that insulating film layer 41. A window 41a is etched at the upper part of the insulating film 41, so that a laser beam can reach the fuse pattern 42 from above the window 41a. Deposited along the rim of the window 41a is a guard ring 43. In order to blow the fuse pattern 42, the laser beam spot is targeted into the window 41a. The fuse pattern 42 is then melted by the energy of the laser beam and becomes open. For reliable operation, fuse patterns should be blown at two spots for each.
Think of, for example, a static RAM (SRAM) device having such fuse patterns as part of its built-in repair function. Actually, there are two ways of arranging fuse patterns and guard rings on a chip, depending on how they are to be used. One way is to provide a guard ring for each individual fuse pattern, and the other is to form a single guard ring shared by a group of several fuse patterns. FIGS. 7(A) and (B) show how guard rings and fuse patterns are arranged in a conventional semiconductor device. Specifically, FIG. 7(A) shows a one-on-one arrangement, while FIG. 7(B) shows a one-on-multiple arrangement.
In the semiconductor device design shown in FIG. 7(A), fuse patterns 51a to 51e have their dedicated guard rings 50a to 50e, one for each. A RAM macro 52 is a group of memory cell arrays, to which a signal is supplied from a signal line 53 through the corresponding fuse patterns 51a to 51e. The RAM macro 52 is designed such that blowing one of the fuse patterns 51a to 51e will interrupt the signal to the corresponding memory cell array, and the function of that memory cell array can be replaced by a redundant memory cell array.
In another semiconductor device design shown in FIG. 7(B), a plurality of fuse patterns 61a to 61e are arranged within a single guard ring 60 to repair, if necessary, a defect in a RAM macro 62, whose function is the same as that of the RAM macro 52 shown in FIG. 7(A). When one of the fuse patterns 61a to 61e is blown, the corresponding memory cell array is disabled because the connection to a signal line 63 is lost. The RAM macro 62 is designed to replace the disabled memory cell array with a redundant memory cell array in itself.
These days, integrated circuits are getting denser and denser, and accordingly, it is desired to reduce the chip space occupied by guard rings and fuse patterns. The fuse pattern arrangement of FIG. 7(A), however, takes up a great deal of chip space since every fuse requires space for a window and a guard ring. While the arrangement of FIG. 7(B) is more efficient than that of FIG. 7(A) in terms of the fuse and guard ring areas, the conductors connecting each fuse pattern with the RAM macro consume a large space. Further, there is a limit to the reduction of its lengthwise dimension, which is indicated by the bidirectional arrow A in FIG. 7(B), because each fuse pattern should be long enough to receive laser beams at two different spots.
In view of the foregoing, an object of the present invention is to provide a semiconductor device in which guard rings and fuse patterns are designed to take up less chip space.
In order to achieve the above object, the invention provides a semiconductor device with fuses for repairing a defect found therein. The semiconductor device comprises: a guard ring; a fuse pattern running in a direction parallel to longitudinal axis of the guard ring; a plurality (n) of branching patterns branching from the fuse pattern and being drawn out of the guard ring in a direction perpendicular to the longitudinal axis of the guard ring; a plurality (n+1) of memory cell arrays, the (n+1)th memory cell array being a redundant memory cell array; a plurality (n) of input/output ports for receiving and sending memory signals; a plurality (n) of switch circuits, coupled to different points on the fuse pattern through the plurality of branching patterns, which switch connection between the input/output ports and memory cell arrays, the ith switch circuit (i=1 . . . n) selecting either the ith memory cell array or the (i+1)th memory cell array, depending on which segment of the fuse pattern is blown.
The above and other objects, features and advantages of the present invention will become apparent from the following description when taken in conjunction with the accompanying drawings which illustrate preferred embodiments of the present invention by way of example.